`timescale 1ns / 1ps

module VDFFE #(
  parameter n = 16
)(
    input wire clk,
    input wire [n-1:0] in,
    input wire load,
    output reg [n-1:0] out
    );
    wire [n-1:0] datain;
    assign datain = load ? in : out;
    always @(posedge clk) begin
        out <= datain;
    end
endmodule
